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E2L0068-19-61 Semiconductor
Semiconductor MSM54V25632A
DESCRIPTION
This version: Jun. 1999 MSM54V25632A Previous version: Sep. 1998
131,072-Word 32-Bit 2-Bank Synchronous Graphics RAM
The MSM54V25632A is a synchronous graphics random access memory organized as 128 K words 32 bits 2 banks. This device can operate up to 100 MHz by using synchronous interface. In addition, it has 8-column Block Write function and Write per bit function which improves performance in graphics systems.
FEATURES
* 131,072 words 32 bits 2 banks memory * Single 3.3 V 0.3 V power supply * LVTTL compatible inputs and outputs * All input signals are latched at rising edge of system clock * Auto precharge and controlled precharge * Internal pipelined operation: column address can be changed every clock cycle * Dual internal banks controlled by A9 (Bank Address: BA) * Independent byte operation via DQM0 to DQM3 * 8-column Block Write function * Persistent write per bit function * Programmable burst sequence (Sequential/Interleave) * Programmable burst length (1, 2, 4, 8 and full page) * Programmable CAS latency (1, 2 and 3) * Burst stop function (full-page burst) * Power Down operation and Clock Suspend operation * Auto refresh and self refresh capability * 1,024 refresh cycles/16 ms * Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (Product : MSM54V25632A-xxAGBK4) xx indicates speed rank.
PRODUCT FAMILY
Family MSM54V25632A-10 MSM54V25632A-12 Clock Frequency MHz (Max.) 100 83 Package 100-pin Plastic QFP (14 20 mm)
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
100 DQ2 99 VSSQ 82 VSSQ 81 DQ29 84 DQ31 83 DQ30 98 DQ1 97 DQ0 96 VCC 95 NC 86 NC 85 VSS 94 NC 93 NC 92 NC 91 NC 90 NC 89 NC 88 NC 87 NC

DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ DQ16 DQ17 VSSQ DQ18 DQ19 VCCQ VCC VSS DQ20 DQ21 VSSQ DQ22 DQ23 VCCQ DQM0 DQM2 WE CAS RAS CS BA (A9) NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36
MSM54V25632A
80 DQ28 79 VCCQ 78 DQ27 77 DQ26 76 VSSQ 75 DQ25 74 DQ24 73 VCCQ 72 DQ15 71 DQ14 70 VSSQ 69 DQ13 68 DQ12 67 VCCQ 66 VSS 65 VCC 64 DQ11 63 DQ10 62 VSSQ 61 DQ9 60 DQ8 59 VCCQ 58 NC 57 DQM3 56 DQM1 55 CLK 54 CKE 53 DSF 52 NC 51 A8
37 38 39 40 41 42 43 44 45 46 47 48
A0 A1 A2 A3 VCC NC NC NC NC NC NC NC NC NC NC VSS A4 A5 A6 A7
100-Pin Plastic QFP
Pin Name A0 - A9 A0 - A8 A0 - A7 A9 DQ0 - DQ31 CS RAS CAS WE Function Address Inputs Row Address Inputs Column Address Inputs Bank Address Data Inputs/Outputs Chip Select Row Address Strobe Column Address Strobe Write Enable Pin Name DQM0 - DQM3 DSF CKE CLK VCC VSS VCCQ VSSQ NC Function DQ Mask Enable Special Function Enable Clock Enable System Clock Input Supply Voltage Ground Supply Voltage for DQ Ground for DQ No Connection
Note:
The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/66
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Semiconductor
MSM54V25632A
BLOCK DIAGRAM
Refresh Counter
Row Decoders
Timing Generator 4Mb Memory Cells Bank - A Sense Amplifiers Column Decoders
Row Decoders
CLK CKE CS RAS CAS WE DSF VCC VSS
Address Buffers
A0 A1 A2
32 I/O Buffers DQ0 to 31
A9
4Mb Memory Cells Bank - B Sense Amplifiers Column Decoders 32
32
DQM0 to 3 Color Register (32 bits) Mask Register (32 bits)
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Semiconductor
MSM54V25632A
PIN DESCRIPTION
CLK CS CKE Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQM0, DQM1, DQM2 and DQM3. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 - RA8 Column address: CA0 - CA7 BA (A9) RAS CAS WE DSF DQM0 DQM3 DQi DSF is part of the inputs of graphics command of the MSM54V25632A. If DSF is inactive (Low level), MSM54V25632A operates just like SDRAM. Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal. Data inputs/outputs are multiplexed on the same pin. 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0, DQM1, DQM2, and DQM3 are invalid. 2. When issuing an active, read or write command, the bank is selected by A9. Functionality depends on the combination. For details, see the function truth table. Selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. A9 = "L" : Bank A, A9 = "H" : Bank B
*Notes:
A9 0 1
Active, read or write Bank A Bank B
3. The auto precharge function is enabled or disabled by the A8 input when the read or write command is issued. A8 0 1 0 1 A9 0 0 1 1 Operation After the end of burst, bank A holds the active status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the active status. After the end of burst, bank B is precharged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A8 and A9 inputs.
A8 0 0 1 A9 0 1 X Operation Bank A is precharged. Bank B is precharged. Both banks A and B are precharged.
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Semiconductor
MSM54V25632A
COMMAND OPERATION
Mode Register Set Command (CS, RAS, CAS, WE, DSF = "Low") The MSM54V25632A has the mode register that defines the operation mode "CAS Latency, Burst Length, Burst Sequence". The mode register is composed of ten bits of memories corresponding to address inputs A0 - A8 and BA. The Mode Register Set command should be executed just after the MSM54V25632A is powered on. Before entering this command, all banks must be precharged. Next command can be issued after tRSC. Special Mode Register Set Command (CS, RAS, CAS, WE = "Low", DSF = "High") The MSM54V25632A has the 32-bit color register for block write operation and the 32-bit mask register for write per bit operation. The Special Mode Register Set command performs loading mask register or color register. When A5 is "high", The mask data presented on the DQ0 - DQ31 is latched into the mask register. When A6 is "high", The color data presented on the DQ0 - DQ31 is latched into the color register. The Special Mode Register Set command must be executed before Masked Block Write and Write Per Bit operations. Next command can be issued after tRSC. Auto Refresh Command (CS, RAS, CAS, DSF = "Low", WE, CKE = "High") The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be performed 1024 times within 16 ms and the next command can be issued after tRC from last Auto Refresh command. Before entering this command, all banks must be precharged. Self Refresh Entry/Exit Command (CS, RAS, CAS, DSF, CKE = "Low", WE = "High") The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left "low". This operation terminates by making CKE level "high". The self refresh operation is performed automatically by the internal address counter on the MSM54V25632A chip. In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be precharged. Next command can be issued after tRC. Single Bank Precharge Command (CS, RAS, WE, DSF, A8 = "Low", CAS = "High") The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA. All Banks Precharge Command (CS, RAS, WE, DSF = "Low", CAS, A8 = "High") The All Bank Precharge command triggers precharge of both bank A and bank B.
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Semiconductor
MSM54V25632A
Bank Active and Masked Write Disable Command (CS, RAS, DSF = "Low", CAS, WE = "High") The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A8 and BA" are strobed. After this command, the write command and block write command for that bank works as the no write per bit operation. Bank Active and Masked Write Enable Command (CS, RAS = "Low", CAS, WE, DSF = "High") The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A8 and BA" are strobed. After this command, the write command and block write command for that bank works as the write per bit operation. Write Command (CS, CAS, WE, DSF, A8 = "Low", RAS = "High") The Write command is required to begin burst write operation. Then burst access initial bit column address is strobed. Write with Auto Precharge Command (CS, CAS, WE, DSF = "Low", RAS, A8 = "High") The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after the burst write. Any command that interrupts this operation cannot be issued. Masked Block Write Command (CS, CAS, WE, A8 = "Low", RAS, DSF = "High") The Masked Block Write command is required to begin block write operation with column mask. The masked block write operation performs writing in the 8 memory cells selected by column addresses "A3 - A7". In this operation, data in color register is written to memory cells with the column mask functions. At the same time, this command can perform write per bit operation. The block write operation is not bursted.
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Semiconductor
MSM54V25632A
Block Write Function
Color Register I/O Mask Column Mask
11001110 11111010 10010011
8 Column 8 DQ Column 7 Column 6 Column 5 Column 4 Column 3 Column 2 Column 1 Column 0 1 1 * * 1 * * 1 1 1 * * 1 * * 1 0 0 * * 0 * * 0 0 0 * * 0 * * 0 1 1 * * 1 * * 1 * * * * * * * * 1 1 * * 1 * * 1 * * * * * * * *
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
Note : Location "*" can not be loaded.
Remark: 1. This diagram shows only for DQ0 - 7. The other DQ is similar as this. Column Mask DQ0 - 7 : Column Mask for DQ0 - 7 DQ8 - 15 : Column Mask for DQ8 - 15 DQ16 - 23 : Column Mask for DQ16 - 23 DQ24 - 31 : Column Mask for DQ24 - 31 Write per Bit Mask data = Mask Register + DQMi DQMi is prior to data of Mask Register.
DQ7
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Semiconductor
MSM54V25632A
Masked Block Write with Auto Precharge Command (CS, CAS, WE = "Low", RAS, DSF, A8 = "High") The Masked Block Write with Auto Precharge command performs precharging at the bank selected by BA automatically after Masked Block Write. Read Command (CS, CAS, DSF, A8 = "Low", RAS, WE = "High") The Read command is required to begin burst read operation. Then burst access initial bit column address is strobed. Read with Auto Prechaege Command (CS, CAS, DSF = "Low", RAS, WE, A8 = "High") The Read with Auto Precharge command is required to begin burst read operation with auto precharge after the burst read. Any command that interrupts this operation cannot be issued. No Operation Command (CS, DSF = "Low", RAS, CAS, WE = "High") The No Operation command does not trigger any operation. Device Deselect Command (CS = "High") The Device Deselect command disables the RAS, CAS, WE, DSF and Address input. This command does not trigger any operation. Data Write/Output Enable Command (DQMi = "Low") The Data Write/Output Enable command enables DQ0 - DQ31 in read or write. The each DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31 respectively. Data Mask/Output Disable Command (DQMi = "High") The Data Mask/Output Disable command disables DQ0 - DQ31. In read cycle output buffers are disabled after 2 clocks . In write cycle input buffers are disabled at the same clock. The each DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31 respectively. Burst Stop Command (CS, WE, DSF = "Low", RAS, CAS = "High") The Burst Stop command stops burst access when the access is in full page. After the Burst Stop command is entered, the output buffer goes into high impedance state.
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Semiconductor
MSM54V25632A
TRUTH TABLE
Command Truth Table
Function Device Deselect No Operation Burst Stop in Full Page Read Read with Auto Precharge Write Write with Auto Precharge Masked Block Write Masked Block Write with Auto Precharge Bank Activate Bank Activate with WPB Enable Precharge Select Bank Precharge All Banks Mode Register Set Special Register Set L L L L L L L L L L L L H H H H L L H H L L L L L H L L L H BA BA BA OP. CODE OP. CODE RA RA L H CS H L L L L L L L L RAS H H H H H H H H CAS H H L L L L L L WE H L H H L L L L DSF L L L L L L H H Address A9 BA BA BA BA BA BA A8 L H L H L H A7 - A0 CA CA CA CA CA CA
DQM Truth Table
Function Data Write/Output Enable Data Mask/Output Disable DQMi L H
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Semiconductor Function Truth Table (1/5)
Current State CS RAS CAS WE DSF Address Idle H L L L L L L L L L L L L L L L Row Active (ACT) H L L L L L L L L L L L L L L L H H H H H H H L L L L L L L L H H H H H H H L L L L L L L L H H H L L L L H H H H L L L L H H H L L L L H H H H L L L L H L L H H L L H H L L H H L L H L L H H L L H H L L H H L L H L H L H L H L H L H L H L H L H L H L H L H L H L H L BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op-Code Op-Code BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op-Code Op-Code NOP or Power Down NOP or Power Down ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Row Active with WPB Row Active ILLEGAL NOP ILLEGAL Auto Refresh/Self refresh Special Register Write Mode Register Write NOP NOP ILLEGAL ILLEGAL ILLEGAL Read Block Write Write ILLEGAL ILLEGAL ILLEGAL Precharge ILLEGAL ILLEGAL Special Register Write ILLEGAL Action
MSM54V25632A
Note 1 Note
2 2 2 2 2
3 4
2
2 2
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Semiconductor Function Truth Table (2/5)
Current State CS RAS CAS WE DSF Address Read (RD) H L L L L L L L L L L L L L L L Write/Block Write H (WT/BW) L L L L L L L L L L L L L L L H H H H H H H L L L L L L L L H H H H H H H L L L L L L L L H H H L L L L H H H H L L L L H H H L L L L H H H H L L L L H L L H H L L H H L L H H L L H L L H H L L H H L L H H L L H L H L H L H L H L H L H L H L H L H L H L H L H L H L BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op-Code Op-Code BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op-Code Op-Code Action
MSM54V25632A
Note 1 Note NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) ILLEGAL 1, 2, 4, 8 Burst Length; ILLEGAL Full Page Burst; Burst Stop AE Bank Active ILLEGAL Term Burst, new Read Term Burst, start Block Write Term Burst, start Write ILLEGAL ILLEGAL ILLEGAL Term Burst, execute Row Precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) ILLEGAL 1, 2, 4, 8 Burst Length; ILLEGAL Full Page Burst; Burst Stop AE Row Active ILLEGAL Term Burst, start Read Term Burst, new Block Write Term Burst, new Write ILLEGAL ILLEGAL ILLEGAL Term Burst, execute Row Precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL 2 2 2 2
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Semiconductor Function Truth Table (3/5)
Current State CS RAS CAS WE DSF Address Read with Auto Precharge (RAP) H L L L L L L L L L L L L L L L Write/Block Write with Auto Precharge (WAP/BWAP) H L L L L L L L L L L L L L L L H H H H H H H L L L L L L L L H H H H H H H L L L L L L L L H H H L L L L H H H H L L L L H H H L L L L H H H H L L L L H L L H H L L H H L L H H L L H L L H H L L H H L L H H L L H L H L H L H L H L H L H L H L H L H L H L H L H L H L BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op- Code Op- Code BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op- Code Op- Code Action
MSM54V25632A
Note 1 Note NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 2 2 2 2 2 2
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Semiconductor Function Truth Table (4/5)
Current State CS RAS CAS WE DSF Address Precharging (PRE) H L L L L L L L L L L L L L L L Refreshing (REF) H L L L L L L L L L L L L L L L H H H H H H H L L L L L L L L H H H H H H H L L L L L L L L H H H L L L L H H H H L L L L H H H L L L L H H H H L L L L H L L H H L L H H L L H H L L H L L H H L L H H L L H H L L H L H L H L H L H L H L H L H L H L H L H L H L H L H L BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op-Code Op-Code BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op-Code Op-Code NOP AE Idle after tRP NOP AE Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP AE Idle after tRP ILLEGAL ILLEGAL Special Register Write ILLEGAL NOP AE Idle after tRC NOP AE Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Action
MSM54V25632A
Note 1 Note
2 2 2 2 2 2 3
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Semiconductor Function Truth Table (5/5)
Current State CS RAS CAS WE DSF Address Mode Register Access (MRA) H L L L L L L L L L L L L L L L Special Mode Register Access (SMRA) H L L L L L L L L L L L L L L L H H H H H H H L L L L L L L L H H H H H H H L L L L L L L L H H H L L L L H H H H L L L L H H H L L L L H H H H L L L L H L L H H L L H H L L H H L L H L L H H L L H H L L H H L L H L H L H L H L H L H L H L H L H L H L H L H L H L H L BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op-Code Op-Code BA, CA, A8 BA, CA, A8 BA, CA, A8 BA, RA BA, RA BA, A8 Op-Code Op-Code NOP NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Action
MSM54V25632A
Note 1 Note
ABBREVIATIONS RA = Row Address CA = Column Address Notes:
BA = Bank Address AP = Auto Precharge
NOP = No OPeration command = High or Low level (Don't care)
1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. NOP to bank precharging or in idle state. Precharges activated bank by BA or A8. 4. Illegal if any bank is not idle.
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Semiconductor Function Truth Table for CKE
Current State (n) CKEn-1 CKEn CS RAS CAS WE DSF Address Self Refresh (SREF) H L L L L L L Power Down (PD) H L L L L L L All Banks Idle (ABI) H H H H H H H H L Any State Other than Listed Above H H L L H H H H H L H H H H H L H L L L L L L L L H L H L H L L L L H L L L L H L L L L L L H H H L H H H L H H H L L L H H L H H L H H L H L L H L H L H L L H L L INVALID Action
MSM54V25632A
Note 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6
Exit Self Refresh AE ABI Exit Self Refresh AE ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down AE ABI Exit Power Down AE ABI ILLEGAL ILLEGAL ILLEGAL NOP (Continue power down mode) Refer to Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension
Notes:
5. If the minimum set-up time tPDE is satisfied when CKE transitions from "L" to "H", CKE operates asynchronously so that a command can be input in the same internal clock cycle. 6. Power-down and self refresh can be entered only when all the banks are in an idle state.
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Semiconductor
MSM54V25632A
Mode Set Address Keys
Operation Code A8 0 0 1 1 A9 0 1 A7 0 1 0 1 TM Mode Setting Reserved Reserved Reserved Length Burst Single Bit A6 0 0 0 0 1 1 1 1 CAS Latency (CL) A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CL Reserved 1 2 3 Reserved Reserved Reserved Reserved Burst Type (BT) A3 0 1 BT Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length (BL) A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8
Write Burst Length
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Special Mode Set Address Keys
A9 0 A8 0 A7 0 A6 LC A5 LM A4 0 A3 0 A2 0 A1 0 A0 0
Load Color (LC) A6 0 1 Function Disable Enable
Load Mask (LM) A5 0 1 Function Disable Enable
Note :
If LC and LM are both high (1), data of Mask and Color register will be unknown.
POWER ON SEQUENCE 1. With CKE = "H", DQM = "H" and the other inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply an Auto-refresh eight or more times. 5. Enter the mode register setting command.
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Semiconductor Burst Length and Sequence BL = 2
Starting Address (column address A0, binary) 0 1 Sequential Type 0, 1 1, 0
MSM54V25632A
Interleave Type Not supported Not supported
BL = 4
Starting Address (column address A1 - A0, binary) 00 01 10 11 Sequential Type 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave Type 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
BL = 8
Starting Address (column address A2 - A0, binary) 000 001 010 011 100 101 110 111 Sequential Type 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4 ,5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Type 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
BL = Full : Sequential only
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Semiconductor
MSM54V25632A
PRECHARGE
Read Interrupted by Precharge CL = 1 CL = 2 or 3 : At the same clock as the last read data. : One clock earlier than the last read data.
BL = 4 0 CLK CL = 1 RD Q1 RD Q1 RD Q1 Q2 Q2 Q2 Q3 PRE Q4 PRE Q3 Q4 PRE Q3 Q4 Hi-Z Hi-Z Hi-Z 1 2 3 4 5 6 7 8
DQ CL = 2
DQ CL = 3
DQ
(tRAS is satisfied)
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Semiconductor
MSM54V25632A
AUTO PRECHARGE
Read with Auto Precharge
BL = 4 0 CLK CL = 1 RAP Q1 RAP Q1 RAP Q1 Q2 Auto precharge starts Q3 Q4 Hi-Z 1 2 3 4 5 6 7 8
DQ CL = 2
Auto precharge starts Q2 Q3 Q4 Hi-Z
DQ CL = 3
Auto precharge starts Q2 Q3 Q4 Hi-Z
DQ
(tRAS is satisfied)
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Semiconductor Write with Auto Precharge
MSM54V25632A
BL = 4 0 CLK CL = 1 WAP D1 WAP D1 WAP D1 D2 D3 D4 D2 D3 D2 D3 Auto precharge starts D4 Hi-Z 1 2 3 4 5 6 7 8
DQ CL = 2
Auto precharge starts D4 Hi-Z
DQ CL = 3
Auto precharge starts Hi-Z (tRAS is satisfied)
DQ
Block Write with Auto Precharge
0 CLK tBWC CL = 1 BWAP Auto precharge starts DB Hi-Z 1 2 3 4 5
DQ
CL = 2
BWAP Auto precharge starts DB Hi-Z
DQ
CL = 3
BWAP DB
Auto precharge starts Hi-Z (tRAS is satisfied)
DQ
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Semiconductor
MSM54V25632A
READ/WRITE COMMAND INTERVAL
Read to Read Command Interval
BL = 4, CL = 2 0 CLK RD-A DQ RD-B QA1 QB1 QB2 QB3 QB4 Hi-Z 1 2 3 4 5 6 7 8
1 cycle
Write to Write Command Interval
BL = 4, CL = 2 0 CLK WT-A DQ DA1 WT-B DB1 DB2 DB3 DB4 Hi-Z 1 2 3 4 5 6 7 8
1 cycle
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Semiconductor
MSM54V25632A
Write to Read Command Interval
BL = 4 0 CLK 1 2 3 4 5 6 7 8
CL = 1
WT-A DA1
RD-B Hi-Z QB1 QB2 QB3 QB4
DQ
1 cycle CL = 2 WT-A DA1 RD-B Hi-Z QB1 QB2 QB3 QB4
DQ
CL = 3
WT-A DA1
RD-B Hi-Z QB1 QB2 QB3 QB4
DQ
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Semiconductor
MSM54V25632A
Block Write to Write/Block Write Command Interval
0 CLK tBWC BW-A DQ DA tBWC BW-A DQ DA WT-B DB1 DB2 BL = 4, CL = 2 DB3 DB4 BW-B DB CL = 2 Hi-Z 1 2 3 4 5 6 7 8
Block Write to Read Command Interval
0 CLK tBWC CL = 1 BW-A DA RD-B Hi-Z tBWC CL = 2 BW-A DA RD-B Hi-Z tBWC CL = 3 BW-A DA RD-B Hi-Z QB1 QB2 QB3 QB4 QB1 QB2 QB3 QB4 QB1 QB2 QB3 QB4 1 2 3 4 5 6 7 8
DQ
DQ
DQ
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Semiconductor Read to Write/Block Write Command Interval
MSM54V25632A
CL = 1, 2, 3 0 CLK RD-A DQM DQ Hi-Z DB1 1 cycle BL = 8, CL = 1, 2 0 CLK CL = 1 RD-A WT-B 1 2 3 4 5 6 7 8 9 DB2 DB3 DB4 WT-B 1 2 3 4 5 6 7 8
DQM DQ QA1 QA2 QA3 QA4 DB1 Hi-Z is necessary WT-B DB2 DB3
CL = 2
RD-A
DQM DQ QA1 QA2 QA3 DB1 Hi-Z is necessary DB2 DB3
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Semiconductor
MSM54V25632A
ex.) CL = 3, BL = 4 0 CLK RD-A DQM DQ QA1 DB1 Hi-Z is necessary DB2 DB3 WT-B 1 2 3 4 5 6 7 8
0 CLK WT-A DQM DQ DA1
1
2
3
DA2
DA3
Note : DQM can mask both data-in and data-out in this special case.
|
4 5 6 RD-B Hi-Z QB2 Note
ex.) CL = 1, BL = 4 7 8 9
QB3
QB4
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Semiconductor
MSM54V25632A
BURST TERMINATION
Burst Stop Command in Full Page
BL = Full Page, CL = 1, 2, 3 0 CLK RD CL = 1 DQ CL = 2 DQ CL = 3 DQ Q1 Q2 Q1 BST Q3 Q2 Q1 Q3 Q2 Q3 Hi-Z Hi-Z Hi-Z 1 2 3 4 5 6 7 8
BL = Full Page, CL = 1, 2, 3 0 CLK WT CL = 1, 2, 3 DQ D1 D2 D3 D4 BST Hi-Z 1 2 3 4 5 6 7 8
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Semiconductor Precharge Termination in READ Cycle
MSM54V25632A
BL = X, CL = 1 0 CLK RD DQ Q1 Q2 Q3 PRE Q4 tRP ACT Hi-Z 1 2 3 4 5 6 7 8
BL = X, CL = 2 0 CLK RD DQ Q1 Q2 PRE Q3 Q4 tRP ACT Hi-Z 1 2 3 4 5 6 7 8
BL = X, CL = 3 0 CLK RD DQ Q1 PRE Q2 Q3 tRP ACT Hi-Z 1 2 3 4 5 6 7 8
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Semiconductor Precharge Termination in WRITE Cycle
MSM54V25632A
BL = X, CL = 1, 2 0 CLK WT DQ D1 D2 D3 D4 PRE D5 tRP ACT Hi-Z 1 2 3 4 5 6 7 8
Note : D5 data will not be written
BL = X, CL = 3 0 CLK WT DQ D1 D2 D3 D4 PRE D5 Hi-Z tRP ACT 1 2 3 4 5 6 7 8
Note : D5 data will not be written
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Semiconductor
MSM54V25632A
ELECTRICAL CHARACTERISTICS
Note : All voltages are referenced to VSS.
Absolute Maximum Ratings
Parameter Voltage on Power Supply Pin Relative to GND Voltage on Input Pin Relative to GND Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VCC, VCCQ VT IOS PD Topr Tstg Condition -- -- -- Ta = 25C -- -- Rating -1.0 to 4.6 -1.0 to VCC + 0.5 4.6 50 1 0 to 70 -55 to 150 Unit V V mA W C C
Caution:
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
(Ta = 0C to 70C) Min. 3.0 2.0 -0.3 Typ. 3.3 -- -- Max. 3.6 VCC + 0.3 0.8 Unit V V V
Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL
Capacitance
Parameter Input Capacitance (A0 - A9) Input Capacitance
(CLK, CKE, CS, RAS, CAS, WE, DSF, DQM)
(VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Symbol CI1 CI2 CI/O Min. -- -- -- Max. 6 6 7 Unit pF pF pF
Input/Output Capacitance (DQ0 - DQ31)
DC Characteristics 1
Parameter Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Symbol VOH VOL ILI ILO IOL = 2 mA 0 V VI 3.6 V; All other pins not under test = 0 V DOUT is disabled, 0 V VO 3.6 V Test Condition IOH = -2 mA Min. 2.4 -- -10 -10 Max. -- 0.4 10 10 Unit V V mA mA
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Semiconductor
MSM54V25632A
DC Characteristics 2
Parameter Operating Current
Symbol
Test Condition Burst length = 1, tRAS tRAS (MIN.), tRP tRP (MIN.), IO = 0 mA
-10 Max. 175 4 3 60
-12 Max. 155 4 3 60
Unit Note mA mA 1
ICC1
Precharge Standby Current ICC2P CKE VIL (MAX.), tCK = 15 ns in Power Down Mode ICC2PS CKE VIL (MAX.), tCK = * CKE VIH (MIN.), tCK = 15 ns, Precharge Standby Current in Non Power Down Mode ICC2NS Active Standby Current in Power Down Mode ICC2N CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = *, Input signals are stable.
mA 30 4 3 70 30 4 3 70 mA 35 35 120 170 230 145 3 240 mA mA mA 3 mA 2 mA
ICC3P CKE VIL (MAX.), tCK = 15 ns ICC3PS CKE VIL (MAX.), tCK = * CKE VIH (MIN.), tCK = 15 ns, ICC3N CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC3NS CKE VIH (MIN.), tCK = *, Input signals are stable. tCK tCK (MIN.), IO = 0 mA CAS Latency = 1 CAS Latency = 2 CAS Latency = 3
Active Standby Current in Non Power Down Mode
Operating Current (Burst Mode) Refresh Current Self Refresh Current Operating Current (Block Write Mode)
130 180 240 165 3 240
ICC4
ICC5 tRC tRC (MIN.) ICC6 CKE 0.2 V ICC7 tCK tCK (MIN.), IO = 0 mA, CAS cycle = 20 ns
Notes 1.
2.
3.
ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
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Semiconductor AC Characteristics Test conditions
MSM54V25632A
* AC measurements assume tT = 1 ns. * Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. * If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX). * An access time is measured at 1.4 V.
2.8 V CLK 1.4 V VSS
2.8 V Input 1.4 V VSS
Output
tCK tCH tSetup tHold tAC tOH 1.4 V
tCL
1.4 V
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Semiconductor Synchronous Characteristics
MSM54V25632A Parameter
Symbol
MSM54V25632A
MSM54V25632A -12 Unit Note Max. (83 MHz) (55 MHz) (28 MHz) 10 15 32 -- -- -- -- 8 12 26 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 Min. 12 18 36 -- -- -- 4 4 3 0 3 3 3 3.5 1.5 3.5 1.5 3.5 1.5 3.5 1.5
-10 Min. Max. (100 MHz) (66 MHz) (33 MHz) 9 13 27 -- -- -- -- 8 12 26 -- -- -- -- -- -- -- -- 10 15 30 -- -- -- 3.5 3.5 3 0 3 3 3 3 1 3 1 3 1 3 1
CAS Latency = 3 tCK3 Clock Cycle Time CAS Latency = 2 tCK2 CAS Latency = 1 tCK1 CAS Latency = 3 tAC3 Access Time from CLK CAS Latency = 2 tAC2 CAS Latency = 1 tAC1 CLK High Level Width CLK Low Level Width Data-out Hold Time Data-out Low-impedance Time Data-out High-impedance Time Data-in Setup Time Data-in Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command (CS, RAS, CAS, WE, DSF, DQM) Setup Time Command (CS, RAS, CAS, WE, DSF, DQM) Hold Time tCH tCL tOH tLZ CAS Latency = 3 tHZ3 CAS Latency = 2 tHZ2 CAS Latency = 1 tHZ1 tDS tDH tAS tAH tCKS tCKH tCMS tCMH
Note
1.
Output load.
1.4 V Z = 50 W Output 30 pF 50 W
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Semiconductor Asynchronous Characteristics
MSM54V25632A Parameter REF to REF/ACT Command Period ACT to PRE Command Period PRE to ACT Command Period Delay Time ACT to READ/WRITE Command ACT (0) to ACT (1) Command Period Data-in to PRE Command Period
Symbol
MSM54V25632A
MSM54V25632A -12 Unit Note Max. -- 120,000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 16 ns ns ns ns ns ns ns ns CLK CLK CLK ns ns ns ns CLK CLK CLK ns ns ns ms Min. 108 72 36 36 24 24 24 24 5 3 2 24 36 36 36 6 4 2 20 10 1 --
-10 Min. Max. -- 120,000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30 16 90 60 30 30 20 20 20 20 5 3 2 20 30 30 30 6 4 2 20 8 1 --
tRC tRAS tRP tRCD tRRD
CAS Latency = 3 tDPL3 CAS Latency = 2 tDPL2 CAS Latency = 1 tDPL1 CAS Latency = 2 tDAL2 CAS Latency = 1 tDAL1 tBWC CAS Latency = 3 tBPL3 CAS Latency = 2 tBPL2 CAS Latency = 1 tBPL1 CAS Latency = 3 tBAL3 CAS Latency = 2 tBAL2 CAS Latency = 1 tBAL1 tRSC tPDE tT tREF
Data-in to ACT (REF) CAS Latency = 3 tDAL3 Command Period (Auto Precharge) Block Write Cycle Time Block Write Data-in to PRE Command Period Block Write Data-in Active (REF) Command Period (Auto Precharge) CKE Setup Time (Precharge Power Down Exit) Transition Time Refresh Time
Mode Register Set Cycle Time
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Semiconductor
MSM54V25632A
TIMING WAVEFORM
AC Parameters for Read Timing (BL = 2, CL = 2)
0 tCK 1 2 3 4 5 6
CLK CKE CS
RAS CAS WE
DSF
z P z
A9 (BA) A8 ADD tAS tAH DQM 0-3 DQ tCMS tCMH tAC Hi-Z tAC tHZ tRCD tRRD tLZ tOH tRAS tOH tRP tRC ACT-A RD-A ACT-B RAP-B PRE-A ACT-A
|| y~ , y ,~ y , | yy , ,y y, ,| zz y z ~, z~ z z ~ ~ P Q PP Q | Q |P y ,Q y , || | | y| ,z yy , P, Q P P~ z z z QQ PP Qz P ~ Q ~ ~~ z Q zP | Q Q ~
7 8 9 10 11 12 13 tCH tCL tCKS tCMS tCMH Auto Precharge Start for Bank B tCKH
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Semiconductor
MSM54V25632A
AC Parameters for Write Timing (BL = 4, CL = 2)
0 1 2 3 4 5 6 7 8 9
y , P Q |~Q ~ | ~ ~ Q P ~ Q ~ ~ | | | y ,Q y~ , P Q P z~ z z P QQ Q P Q P ~ | Q | ~Q | Q~ y~ , yQ ,~ |z y , Q P ~ Q P ~ z ~ z Q ~ Q ~ ~ | y , y , | y , | | z z PQ ~ P
10 11 12 13 14 15 16 17 18 19 20 21 CLK CKE CS tCKS tCMS tCMH Auto Precharge Start for Bank A Auto Precharge Start for Bank B tCKH RAS CAS WE DSF A9 (BA) A8 ADD tAS tAH DQM 0-3 DQ tCMS tCMH Hi-Z tDS tDH tRCD tRRD tDAL tDPL tRP tRC ACT-A WAP-A ACT-B WAP-B ACT-A WAP-A PRE-A ACT-A
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Semiconductor Relationship between Frequency and Latency
Rate Clock Cycle Time [ns] Frequency [MHz] CAS Latency [tRCD] RAS Latency (CAS Latency + [tRCD]) [tRC] [tRAS] [tRRD] [tRP] [tDPL] [tDAL] 10 100 3 3 6 9 6 2 3 2 5 MSM54V25632A-10 15 66 2 2 4 6 4 2 2 2 3 30 33 1 1 2 3 2 1 1 1 2 12 83 3 3 6 9 6 2 3 2 5
MSM54V25632A
MSM54V25632A-12 18 55 2 2 4 6 4 2 2 2 3 36 28 1 1 2 3 2 1 1 1 2
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Semiconductor Power on Sequence and Auto Refresh (Initialization)
0 CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ High level is necessary 1 2 3 4 5 6 7 8 9
MSM54V25632A
10 11 12 13 14 15 16 17 18 19 20 21
8 refresh cycles are necessary
High level is necessary Hi-Z
| | y , y , z~ z y~ ,z y , ~ z z ~ z z P Q P Q | |Q y~ , PQ zP ~ z y , Q P ~P zz Q ~
ADDRESS KEY
REF PRE (All Banks) tRC
REF
MRA
tRC
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Semiconductor
MSM54V25632A
Mode Register Set (BL = 4, CL = 2)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
| y , P| |y z y , PQ z~ , Q ~ P | z y , Q P ~ z | Q PP |~ Q ~ P | |z ~ y , z~ yz , | y | ,y | , | | z y|Q ~ P , ~ ~ z y , | z y , | z
CLK CKE CS H tRSC (20 ns) RAS CAS WE DSF A9 (BA) A8
ADDRESS KEY
ADD
DQM 0-3 DQ
Hi-Z
PRE MRA (All Banks) tRP
ACT
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Semiconductor Auto Refresh (CL = 2)
0 CLK CKE CS 1 2 3 4 5 6 7 8 9
MSM54V25632A
10 11 12 13 14 15 16 17 18 19 20 21
| z y , z ~ z |~ y , |~ | yQ ,~ |~ P~ z Q P | P Q P | yP ,~ yz , y , y , y ,z | y Q ~ , z P zQ zQ ~ P | z y , P z z P Q Q
H RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ L Q1 PRE REF REF ACT RD tRP tRC tRC
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Semiconductor
Self Refresh (Entry and Exit)
0 1 2 3 4
| y , | y , y , z y~ , z yz ,z | z yz z , z~ y| , | y~ , |P zz y P ,z y , z Q ~ Q ~ | | P | P Q ~
MSM54V25632A
7 8 9 10 11 12 17 18 19 20 21 L PRE SREF entry SREF Exit SREF entry or (ACT) Next clock enable tRC SREF Exit ACT Next clock enable tRC tRP
CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ
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Semiconductor
MSM54V25632A
Auto Precharge after Read Burst (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
ACT-A
| |y y , ,z y , zz z z y~ ,z y , ~ ~ | P Q Q P P Q |z |Q P ~ y , | y ,~ y , yQ ,~ P | zy | , zz z ~ z ~ Q ~
H RAa RBa RBb RAa CAa RBa CBa CAb RBb CBb L Hi-Z QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBa3 QBa4 QAb1 QAb2 QAb3 QAb4 QBb1 QBb2 ACT-B RAP-A RAP-B AP-A RAP-B RD-A AP-B ACT-B
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Semiconductor
MSM54V25632A
Auto Precharge after Write Burst (BL = 4, CL = 3)
0 1 2 3 4 5 6 7 8 9
| | Q y~ , yQ ,~~ Q P ~ ~ z z Q ~ ~ y , z z P | y , | y , | | |~ y ,~ y , |Q Q~ ~ z z Q P ~ ~ Q ~ y , | y , | y , z z P | y , | Q Q P Q P
10 11 12 13 14 15 16 17 18 19 20 21 CLK CKE CS H RAS CAS WE DSF A9 (BA) A8 RAa RAa L RBa RBb ADD CAa RBa CBa CAb RBb CBb DQM 0-3 DQ Hi-Z DAa1 DAa2 DAa3 DAa4 DBa1 DBa2 DBa3 DBa4 DAb1 DAb2 DAb3 DAb4 DBb1 DBb2 DBb3 DBb4 ACT-A ACT-B WAP-A ACT-B WAP-B WT-A WAP-B AP-B AP-A
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Semiconductor
MSM54V25632A
Full Page READ Cycle (CL = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
y , y, ,z y , y , z y | y , | y , |Q y ,z yP , |P y ~ , yQQ ,~ ~ Q | z y , z y , z Q P P | y , | , yz , | y Q , |~ Q y~ ,~ ~ ~ | | y , z y , | y , z | z y Q P P
CLK CKE CS H RAS CAS WE DSF A9 (BA) A8 RAa RAa L RBa RBa RBb ADD CAa CBa RBb DQM 0-3 DQ Hi-Z QAa QAa+1 QAa-3 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 ACT-A RD-A ACT-B RD-B Burst cannot end in Full Page mode Burst stop Command PRE-B ACT-B tRP
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Semiconductor Full Page WRITE Cycle (CL = 3)
0 CLK CKE CS H 1 2 3 4 5 6 7 8 9
MSM54V25632A
10 11 12 13 14 15 16 17 18 19 20 21
~ | | y , z | yQ ~ , z ~ P z z Q |P ~ yz , ~ z P yz , Q P ~ Q ~ | | y , y , yQ , z~ z z Q z Q P z~ z y , y , y ,P ~z z ~ P Q P
RAS CAS WE DSF A9 (BA) A8 RAa RAa L RBa RBa RBb ADD CAa CBa RBb DQM 0-3 DQ Hi-Z DAa DAa+1 DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4 ACT-A WT-A ACT-B Burst cannot end in Full Page mode WT-B Burst stop Command tRP PRE-B ACT-B
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Semiconductor
MSM54V25632A
PRE (Precharge) Termination of Burst (BL = 2, 4, 8, Full, CL = 3)
0 CLK CKE CS RAS CAS WE H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
z z ~ z z ~ | y , y , | z y ~ , z y~ , P Q P ~ ~ z ~ z Q ~ z ~ ~ | y , | | z y , P | Q ~ z Q y ,Q z~ y , P Q P Q P P
DSF A9 (BA) A8 RAa RAb RAb RAc ADD RAa L CAa CAb RAc DQM 0-3 DQ DAa1 DAa2 QAb1 QAb2 QAb3 Hi-Z ACT-A WT-A RD-A PRE-A PRE Command Termination tRCD ACT-A PRE Command Termination tRAS PRE-A ACT-A tDPL tRP tRP
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Semiconductor
MSM54V25632A
Clock Suspension during Burst Read (using CKE Function) (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
RAa RAa L
ACT-A
| y| z ,y | z y , z , z~ ~ |P y| z y , P | z y , P z , PQ z~ Q ~
CAa QAa1 QAa2 QAa3 QAa4 RD-A 1-CLOCK 2-CLOCK SUSPENDED SUSPENDED 3-CLOCK SUSPENDED Hi-Z (turn off) at end of burst
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Semiconductor
MSM54V25632A
Clock Suspension during Burst Write (using CKE Function) (BL = 4, CL = 3)
0 CLK CKE CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
P | z y , |Q y~ , PP zz QQ PP ~~ zz y , z y , P| | z y| | y , , zQ ~ z |P yz , Pz z z QQ PP ~~ zz
RAS CAS WE DSF A9 (BA) A8 RAa RAa ADD CAa DQM 0-3 DQ L DAa1 DAa2 DAa3 DAa4 ACT-A 1-CLOCK 2-CLOCK SUSPENDED SUSPENDED WT-A 3-CLOCK SUSPENDED
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Semiconductor
MSM54V25632A
Power Down Mode and Clock Suspension (BL = 4, CL = 2)
0 1 2 3 4 5 6 7 8 9
y~ ,P | yQ Q~ ,P |~ Q ~ | | y , | | y , | z ~ Q ~ ~ z ~ Q ~ | ~ ~ | | P Q ~ Q P ~ Q ~ || | y yQ ,,~ yy ,, yz ,~ ~ z z | y , y ,Q z~ ~
10 11 12 13 14 15 16 17 18 19 20 21 CLK CKE CS tCKS tPDE VALID RAS CAS WE DSF A9 (BA) A8 RAa RAa ADD CAa DQM 0-3 DQ L QAa1 QAa2 QAa3 QAa4 ACT-A RD-A PRE-A PD Entry PD Exit Clock Mask Start Clock Mask End PD PRECHARGE STANDBY PD ACTIVE STANDBY
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Semiconductor
MSM54V25632A
CLOCK Suspend Exit & Power Down Exit
1) Clock Suspend (= Active Power Down) Exit CLK CKE
Internal CLK
Command
Notes: 1. 2. 3. 4.
,
CLK tCKS
Note 1
2) Power Down (= Precharge Power Down) Exit
(CASE 1) CKE Internal CLK
Note 3
tPDE
Note 2
RD
Command (CASE 2) CKE Internal CLK
ACT < tPDE
Note 4
Note 2
Command
NOP
ACT
Active power down: one or both bank active state. Precharge power down: both bank precharge state. tPDE: Asynchronous AC parameter. Time for Power Down Exit Setup Time. Only valid at precharge power down exit. tCKS < tPDE, NOP should be issued. And new command can be issued after 1 Clock.
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Semiconductor Byte Read/Write Operation (by DQM) (BL = 4, CL = 2)
0 1 2 3 4 5 6 7 8 9
MSM54V25632A
| y , yQQ ,~~ | y , y , y , | y , Q ~ z Q P ~ z ~ P zP Q zP ~ QQ Q P Q P | y ,QQ y~~ , | y , y , | y , y , Q P ~ z Q Q~ ~ z PP z z z Q P z~
10 11 12 13 14 15 16 17 18 19 20 21 CLK CKE CS H RAS CAS WE DSF A9 (BA) A8 RBa ADD RBa CBa CBb CBc DQM0 DQM DQM1 DQ 0-7 QBa1 QBa2 QBa3 DBb2 DBb3 QBc2 QBc3 DQ 8 - 15 QBa2 QBa3 QBa4 DBb1 DBb2 DBb4 QBc1 QBc2 QBc3 QBc4 ACT-B RD-B Byte of DQ8 - 15 not Read Byte of DQ0 - 7 not Read Byte of RD-B DQ8 - 15 not Write Byte of DQ0 - 7 not Read Byte of DQ0 - 7 not Read Byte of DQ0 - 7 not Write Byte of DQ0 - 7 not Write WT-B
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Semiconductor
MSM54V25632A
Burst Read and Single Write (BL = 4, CL = 2)
0 CLK CKE CS H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
| | Q ~ y , ~ y , | PQ |~ ~ P | z y | ,y | z, yP Q ,~ | y z , z ~ y , zP z | y , Q ~ Q y , z y ,Q zQ ~ P | z yQ Q y ,, |z y Q ,~ P z | PP PQ yP ,z Q P P
RAS CAS WE DSF A9 (BA) A8 RBa RBa ADD CBa CBb CBc CBd CBe DQM0 DQM1 DQ 0-7 DQ 8 - 15 QBa1 QBa2 QBa3 QBa4 DBb
Write Masking
DBe
DBc ACT-B RD-B Single WT Single WT RD
QBd1 Single WT
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Semiconductor
MSM54V25632A
Special Mode Register Set (BL = 4, CL = 2)
0 CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
DQM 0-3 DQ
| y ~ ,z | y , z~ | y , | z y , z ~ |z y Q P ,~ |z y , P z z yQ ,~ y , y , z z y ,z z y , | y , z y , P | z y , z y , P z Q ~
H tRSC (20 ns)
ADDRESS KEY Color or Mask data
Hi-Z
PRE SMRA (All Banks) tRP
ACT is valid
Remark Special Register Set command can be input at any state.
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Semiconductor
MSM54V25632A
Random Row Write with WPB (BL = 8, CL = 3)
0 CLK CKE CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
y ,z y , zz y ,z z y , y , z ~ | |Q Q | y ~ , | Q P ~ yz , y ,~ z zQ ~ yQ , | y , y , P z z ~ z P P Q Q P P | | z | ~ | Q P~ yQ ,~ y , z~ | | y , ~ z P Q P ~
H RAS CAS WE DSF A9 (BA) A8 RAa RAa RBa RBa RAb RAb ADD CAa CBa CAb DQM 0-3 DQ L DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2 DAb3 ACT-A WT-A with WPB WPB is enabled. tRCD ACT-B WT-B PRE-A WPB is disabled. tDPL tRP ACT-A WT-A PRE-B WPB is disabled. tDPL
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Semiconductor
MSM54V25632A
Block Write (Page at Same Bank) (CL = 3)
0 CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
| || y ~ , z z z y , | ~ z | y , zz ~~ z ~ y~ , y ,~ z ~ | | y , |~ |~ z | y , yz , | | y ,| yy , ~, y , ~ zz z zz y z, z | Q~ P ~~ Q P~ y ,Q z ~ ~ z zQ ~ P Q Q QP P~ | P Q P
RBa RBa RBb CBa CBb CBc CBd RBb CBc
I/O Mask I/O Mask I/O Mask I/O Mask I/O Mask L = No I/O Mask
CM
CM
CM
CM
CM
ACT-B
BW-B
BW-B
BW-B
BW-B
PRE-B
ACT-B BW-B with WPB WPB is enabled. tRP tRCD
tRCD
tBWC
tBWC
tBWC
tBPL
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Semiconductor
MSM54V25632A
Block Write (Page at Same Bank) Changing Color and Mask Data (CL = 3)
0 1 2 3 4 5 6 7 8 9
yz , yz , y , y , y , z y , z z | | Qz |P Q y~ ,P y ,~~ y ,~~ | | y , | y , y , z z z P | | | y , y , y , Q P ~ ~ ~ z z P z z Q ~ z ~ Q ~ ~ Q Q z |Q ~~ | ~ y~ , | y , | P | | y , P Q P ~ z ~ z P Q Q PP Q Q Q ~ ~ Q P Q P Q Q
10 11 12 13 14 15 16 17 18 19 CLK CKE CS H RAS CAS WE DSF A9 (BA) A8 RBa RBa RBb ADD CBa 20h CBb 40h CBc CBd RBb DQM 0-3 DQ
I/O Mask I/O Mask I/O Mask I/O Mask
CM
Mask
CM
Color
CM
CM
ACT-B with WPB
BW-B
SMRA BW-B SMRA BW-B (Mask data) (Color data) tRSC (20 ns) tBWC tRSC (20 ns)
BW-B
PRE-B
ACT-B
tRCD
tBWC
tBWC
tBPL
tRCD
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Semiconductor Interleaved Block Write (CL = 3)
0 CLK CKE CS RAS CAS WE H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MSM54V25632A
16
17
18
19
z y , y , zz y z , | z y , | z y , | P Q P P ~| z zy z , yz ,y ~ , ~Q ~ P ~ | y ,Q Q Q ~ zQ ~ ~ z P P Q P Q | P | | y , | z y , P z Q P P ~ Q Q~ ~ ~| zz y ~, Q |~
DSF A9 (BA) A8 RAa RAa RBa RBb ADD CAa RBa CBa CAb CBb RBb DQM 0-3 DQ L
Column Mask
CM
CM
CM
CM
ACT-A
ACT-B
PRE-B
ACT-B
BW-A tRCD tRCD
BW-B
BW-A tBWC
BW-B tBWC tBPL tRP
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Semiconductor Random Column Read (Page with Same Bank) (BL = 4, CL = 3)
0 1 2 3 4 5 6 7 8 9
MSM54V25632A
|| y ,z~ | yzQ ,~ | | y , y , y , | y , Q P Q P ~ ~ P Q z Q ~ ~ z Q Q P~ Q Q ~ ~ z Q P Q P Q | QQ y~ , y~ , y , | y , | y , y , Q P ~ z z Q zQ P~ Q ~
10 11 12 13 14 15 16 17 18 19 20 21 CLK CKE CS H RAS CAS WE DSF A9 (BA) A8 RAa RAa RAa ADD CAa CAb CAc RAa CAa DQM 0-3 DQ L QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 RD-A PRE-A ACT-A RD-A ACT-A RD-A RD-A tRP
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Semiconductor Random Column Write (Page with Same Bank) (BL = 4, CL = 3)
0 CLK CKE CS H 1 2 3 4 5 6 7 8 9
MSM54V25632A
10 11 12 13 14 15 16 17 18 19 20 21
yz , y ,z z y z , zz y z ,y z , z |z y ,~ yz , y , Pz | z yz P ,P z yP | ,z zy y , z , zQ zQ P Q P Pz z P~ Q P |z PP | P | z |y z y ,, |~ y ,Q P~ zQ P ~ z Q P ~ P P PQ
RAS CAS WE DSF A9 (BA) A8 RBa RBd ADD RBa CBa CBb CBc RBd CBd DQM 0-3 DQ ACT-B L DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4 WT-B WT-B WT-B PRE-B tRP ACT-B DBd1 WT-B
58/66
Semiconductor Random Row Read (BL = 8, CL = 3)
0 CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ ACT-B tRCD RD-B CL H 1 2 3 4 5 6 7 8 9
MSM54V25632A
10 11 12 13 14 15 16 17 18 19 20 21
RBa RBa
| y~ , | ~ z~ z z y ,~ | y z , z || zz yy ,, z z z P Q P P Q P Q P z y ,Q |P y~ , P zP | zQ y~ Q , |~ z z P~ | P | z zy y , P , z P
RAa RBb CBa RAa CAa RBb CBb L QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8 ACT-A RD-A PRE-B tRP ACT-B RD-B PRE-A
59/66
Semiconductor
MSM54V25632A
Random Row Write (BL = 8, CL = 3)
0 CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
RAa RAa
ACT-A
| | y , ~ | | z y , ~ ~ z z ~ z ~ z y ,~ z y~ , Q P | y , | Q ~ P y , z ~ ~ Q P ~ z Q P | ~ PQ ~ z y~ , PQ Q |~
RBa RBa RAb RAb CAa CBa CAb L DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2 DAb3 ACT-B WT-B PRE-A ACT-A WT-A WT-A PRE-B tRCD tDPL tRP tDPL
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Semiconductor READ and WRITE (BL = 4, CL = 3)
0 CLK CKE CS 1 2 3 4 5 6 7 8 9
MSM54V25632A
10 11 12 13 14 15 16 17 18 19 20 21
| P | P z z y z , || z y y , | y, Q ,~ | y ~ , y , P z Q P ~ ~ z z z P | Q |~ | y ~ , | yP , zQ P ~ y , y , zP | z z z y , z | z y , ~ z
H RAS CAS WE DSF A9 (BA) A8 RAa ADD RAa CAa CAb CAc DQM 0-3 DQ ACT-A RD-A Write latency = 0 DAb1 DAb2 WT-A
Write Masking
QAa1 QAa2 QAa3 QAa4
DAb4 RD-A
QAc1 QAc2 Hi-Z
0-clock latency Hi-Z at the end of Burst function 2-clock latency
61/66
Semiconductor
MSM54V25632A
Interleaved Column READ Cycle (BL = 4, CL = 3)
0 1 2 3 4 5 6 7 8 9
yQ ,Q yQ ,~~ |Q ~~ | Q Q ~ z y , z | | y , y , P P P P | y , | ~ z zQ ~ ~ Q P P Q | |Q Q y~ ,Q |~ y~ , Q Q | y , y , | z P P ~ Q ~ z y , z | y , z P P QQ ~
10 11 12 13 14 15 16 17 18 19 20 21 CLK CKE CS H RAS CAS WE DSF A9 (BA) A8 RAa RBa ADD RAa CAa RBa CBa CBb CBc CAb DQM 0-3 DQ L QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBb1 QBb2 QBc1 QBc2 QAb1 QAb2 QAb3 QAb4 RD-B RD-B RD-B RD-A PRE-B PRE-A ACT-A RD-A ACT-B tRCD tRRD CL
62/66
Semiconductor
MSM54V25632A
Interleaved Column WRITE Cycle (BL = 4, CL = 3)
0 CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
| z ~ | ~ | y~ , |~ y ,~ ~z ~ z ~ z Q PQ Q Q P~ ~ ~ z ~ ~ y , z~ zQ P Q |P | ~ y , ~ | Q | Q P P Pz
RAa RBa RAa CAa RBa CBa CBb CBc CAb CBd L DAa1 DAa2 DAa3 DAa4 DBa1 DBa2 DBb1 DBb2 DBc1 DBc2 DAb1 DAb2 DBd1 DBd2 DBd3 DBd4 WT-B WT-B WT-B WT-A WT-B PRE-A tDPL tDPL ACT-A WT-A ACT-B tRCD tRRD PRE-B
63/66
Semiconductor
MSM54V25632A
Full Page Random Column Read (BL = Full Page, CL = 2)
0 CLK CKE CS RAS CAS WE DSF A9 (BA) A8 ADD DQM 0-3 DQ ACT-A ACT-B RD-B RD-A RD-B RD-A RD-B PRE-B (PRE Termination) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
H
L
|, y~ , |~ z y | y ,, z | z y Q P Q | z | z yz Q ,~ z y~ , P | y | , |P y P , y ,Q P P | | z y , z y , ~ ~
RAa RBa RAa RBa CAa CBa CAb tRCD tRRD tRCD CBb CAc CBc QAa1 QBa1 QAb1 QAb2 QBb1 QBb2 QAc1 QAc2 QAc3 QBc1 QBc2 QBc3 Hi-Z RD-A
64/66
Semiconductor
MSM54V25632A
Full Page Random Column Write (BL = Full Page, CL = 2)
0 CLK CKE CS H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
z y , y , yz , zz P PQ ~ | | y , y , y , | z z zQ P ~ P | Q |Q ~ y , yP , yP , | zz y z ,z z y ~ , z y P ,z P P Q PP | | ~ |~ |Q | ~ |~ P
RAS CAS WE DSF A9 (BA) A8 RAa RBa ADD RAa DQM 0-3 DQ L RBa CAa CBa CAb tRCD tRRD tRCD CBb CAc CBc DAa1 DBa1 DAb1 DAb2 DBb1 DBb2 DAc1 DAc2 DAc3 DBc1 DBc2 DBc3 WT-B WT-B WT-A WT-B ACT-A ACT-B PRE-B (PRE Termination) WT-A WT-A
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Semiconductor
MSM54V25632A
PACKAGE DIMENSIONS
(Unit : mm)
QFP100-P-1420-0.65-BK4
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.54 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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E2Y0002-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan

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